Embodiments of the present disclosure relate to a test mode control circuit, and more particularly to a technology for controlling a vendor specific test mode.
Generally, a register set (RS) is used to define special functions from among DDR SDRAM operations. RS may include Mode Register Sets (MRS) and Extend Mode Register Sets (EMRS).
In MRS and EMRS, a mode register setting command and special modes of the DDR SDRAM operations are established as values applied to address pins. The established MRS and the established EMRS may remain unchanged until they are re-programmed or until they are powered off.
The MRS are mainly requisite for a synchronous dynamic random access memory (DRAM) and a static random access memory (SRAM). Prior to using the chip, the mode setting is achieved, such that a burst type, a burst length (BL), column address strobe (CAS) signal latency (CL), etc. are established.
For example, the MRS select and use a test mode which involves a vendor testing the chip and a Joint Electron Device Engineering Council (JEDEC) mode where a user decides a burst type, a burst length, etc.